PRISM Forum

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Posted by: Sue Hedrick (shedrick@advanced-control.com )
Organization:ACC
Date posted: Wed May 3 16:43:04 US/Eastern 2006
Subject: Resistor calculation
Message:
With regard to resistor calculations, how can I determine theta EC. I had thought that it was calculated using (storage temp - max operating temp) / resistor power rating. This gives me huge numbers, greater than 600 deg C / W. What should I be doing?
Thanks, Sue

Replies: (list all replies)
Theta-EC
David Dylis Thu May 4 8:34:14 US/Eastern 2006
Resistor calculation
Sue Hedrick Thu May 4 10:28:39 US/Eastern 2006
Resistor Temperature/Temperature Rise
David Dylis Thu May 4 10:47:56 US/Eastern 2006

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Posted by: Tom Brennom (tbrenno@rockwellcollins.com )
Organization:Rockwell Collins
Date posted: Tue Feb 28 9:12:29 US/Eastern 2006
Subject: Component Model Failure Rates
Message:
Can you tell me how often component model base failure rates are updated? I realize that publications such as EPRD-97 and NPRD-95 document component failure rates. But, how often are those of PRISM updated? One of the old challenges of -217 was always trying to keep up with the changing IC technologies and failure rates.

Replies:
PRISM Updates
bwd Tue Feb 28 10:25:09 US/Eastern 2006

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Posted by: Ralph Listl (ralph.listl.t-systems@eads.com )
Organization:EADS
Date posted: Mon Feb 27 5:36:41 US/Eastern 2006
Subject: Dormant Temperature
Message:
One of the environment factors that is used for calculation is the dormant temperature. If this value is changed (leaving all other parameters unchanged)is has influence on the overall reliability. Could you please give a detailed explanation (formula) where the dormant temperature influences the failure rate and how it is used within the model (what conditions/assumptions are used). Currently we are in a project where this temperature is not defined and we need an understanding which value we should choose for our calculation.

Replies: (list all replies)
Temperature dependency
David Dylis Tue Mar 6 5:19:00 US/Eastern 2007
Temperature Dependency
Ralph List Tue Mar 6 5:20:19 US/Eastern 2007
Temperatue Dependancy
David Dylis Tue Mar 6 5:22:14 US/Eastern 2007

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Posted by: Ralph Listl (ralph.listl.t-systems@eads.com )
Organization:EADS
Date posted: Mon Feb 27 5:27:44 US/Eastern 2006
Subject: Prism Reliability Model
Message:
The Prism Reliability Model uses an initial failure rate multiplied by a process grade factor. The calculation of the inital failure rate for all via RACrates model supported items (Capacitors, Resistors...) makes use of a temperature dependent factor in their models. Therefor all base failure rates are temperature dependent. The process grade factor does also include an environment factor that is temperature dependent. If a complete system has been set up and the temperature is changed it influences the base failure rates as well as the process grade factor.
From my point of view a temperature dependency should either be applied on the base failure rate or for the process grade factor but not on both, because this is double influence. A temperatue dependence on item level is understandable, but a temperature dependence on a process grade is for my understanding not correct. Could you please explain why the Prism model is set up like this?

Replies: (list all replies)
Temperature dependency
David Dylis Mon Feb 27 15:19:02 US/Eastern 2006
Temperature Dependency
Ralph Listl Tue Feb 28 7:40:15 US/Eastern 2006
Temperatue Dependancy
David Dylis Tue Feb 28 9:52:18 US/Eastern 2006

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Posted by:Thomas Urbanczyk (thomas.urbanczyk "at" systema-gmbh.de )
Organization:Systema Engineering
Date posted: Fri Jan 20 5:14:35 US/Eastern 2006
Subject: IC,Memory/Microprocessor Model
Message:
By performing a MTBF FaultTree breakdown (PRISM was used for MTBF data input), I noticed the following issue regarding the IC,Memory/Microprocessor Model as utilized for main processors:
How is it possible, that the PRISM model of a highly complex microprocessor (e.g. Freescale PowerPC) will deliver a lower (baseline) item failure rate as the PRISM model of a lowcost And-Gate? Both components has been modelled with the same parameters. I would expect the defect rate of the microprocessor significant higher. Could you please explain this circumstance? Could you furthermore make a proposal, how to represent the complexity of such highly complex ICs versus simple AND-Gate ICs with the given options in PRISM? Best regards, Thomas Urbanczyk

Replies: (list all replies)
IC Memory/Microprocessor model
David Dylis Tue Jan 31 9:11:32 US/Eastern 2006
Reply
Thomas Urbanczyk Thu Feb 2 2:59:45 US/Eastern 2006

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