Forum: Reliability & Maintainability Questions and Answers

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Posted by: Sathees kumar Ramamoorthy (satheeskr@ctd.hcltech.com )
Date posted: Thu Apr 3 9:26:44 US/Eastern 2003
Subject: Derating
Message:
I'll be grateful if anybody could help me in solving this issue and other issues that I have posted in this forum.

Question :" Whether we have to use the Derated power as the Rated power if we are using the device above the ambient temperature". For eg., 0.0088 W/'C is the derating to be done for a diode whose rated power is 0.65 W (at 25'C). If I'm using the device at 70'C, the derated power comes to 0.254 W which is 71% derating. Now whether I have to use Derated or Rated power for my stress calculation.
Please clarify. Thanks in advance. Sathees.

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Posted by: Sathees kumar Ramamoorthy (satheeskr@ctd.hcltech.com )
Organization:HCL Technologies
Date posted: Thu Apr 3 9:28:42 US/Eastern 2003
Subject: Reg - MIL HDBK 217FN2
Message:
Dear Sir, I would like to be get clarified about three issues that I have faced in MIL HDBK 217FN2.


1. For computing Voltage stress factor(Pi S) (page 6.7) for Transistors, Applied Vce and Rated Vceo are required. Whether this Applied Vce has to be calculated when the Transistor is conducting or when it is in Cut-off state.

2. For computing Electrical stress factor(Pi S) (page 6.3) for Diodes(Low Frequency) Voltage stress ratio is required. It is mentioned in MIL HDBK 217FN2 that "Voltage is diode reverse voltage". I would like to get it confirmed that Voltage Applied and Voltage Rated both refer to Reverse voltage.

3. Power Dissipation is required for computing Power factor(Pi P) (page 9.2) for Resistors. Does this Power dissipation refer to Rated or Actual Power dissipation.
Please clarify. Regards,Sathees.

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Posted by: Heu Yon Chung (heu_yon_chung@yahoo.co.uk )
Date posted: Sat Mar 22 2:45:28 US/Eastern 2003
Subject: Chinese Standards B299
Message:
I am looking for a copy of this standard to read. Can anybody help. thank you

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Posted by: Sathees kumar Ramamoorthy (satheeskr@ctd.hcltech.com )
Date posted: Fri Mar 21 13:49:56 US/Eastern 2003
Subject: FMEA
Message:
Hello,
Is it neccessary to do FMEA pin wise for a 100 pin PLD or could we limit upto the failure modes given in the FMD97 tool. I'm also not clear whether failure mode of chip will also include short/open circuit of its input/output pins or only modes like manufacturing defects, internal short/open. Please clarify.

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Posted by: Richard Smith
Date posted: Tue Mar 18 10:22:38 US/Eastern 2003
Subject: CHR Capacitor Shelf Life/Aging
Message:
Can anybody please refer me to a source of information on Capacitor Aging and Shelf Life (aging mechanisms and reliability of older components).
I am particularly interested in CHR capacitors (fixed, metallized, plastic film dielectric). Thanks in advance.

Replies: (list all replies)
Film Capacitor Life
BWD Tue Mar 18 11:45:17 US/Eastern 2003
CHR Capacitor Shelf Life
Richard Smith Tue Mar 18 14:14:38 US/Eastern 2003
Capacitor Non-op Degradation
BWD Wed Mar 19 10:44:44 US/Eastern 2003

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