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Forum: Reliability & Maintainability Questions and Answers

Topic: Reliability & Maintainability Questions and Answers

Topic Posted by: Reliability & Maintainability Forum (src_forum@alionscience.com )
Organization: System Reliability Center
Date Posted: Mon Aug 31 12:47:36 US/Eastern 1998

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Original Message:

Posted by: CAR
Date posted: Tue Aug 29 10:31:44 US/Eastern 2000
Subject: Semiconductor Wafers / Dies
Message:
Could anybody preovice guidance on how to claculate generic failure rates for semiconductor wafers and dies. Thanks in advance


Reply:

Subject: Semiconductor Wafer/Die Failure Rates
Reply Posted by: Bruce Dudley (bdudley@alionscience.com )
Organization: Reliability Analysis Center
Date Posted: Wed Sep 13 11:58:46 US/Eastern 2000
Message:
Determining the actual die failure rate is difficult as the data base is only from short duration high stress testing or from component activation tests. At the RAC, we developed a new prediction tool called "PRISM". In this tool, failure rates for the base operating die are included. This subset of the general microcircuit model includes conditions for digital gates, microprocessor/memories and linear devices. Die failure rates from the PRISM model in failures per billion hours (fits) are as follows; Digital Gate (25 degrees C)- 0.09, (40 C)- 0.363 Memory/Microprocessor (25 C)- 0.2, (40 C)- 0.76 Linear (25 C)- 0.52, (40 C)- 1.85 For wafer scale, we do not have any failure data. My recommendation would be to use the die factor times the numer of used die on the wafer.


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