SRC Forum - Message Replies

Forum: Reliability & Maintainability Questions and Answers

Topic: Reliability & Maintainability Questions and Answers

Topic Posted by: Reliability & Maintainability Forum ( )
Organization: System Reliability Center
Date Posted: Mon Aug 31 12:47:36 US/Eastern 1998

Back to message list Show all replies Topics List About this forum
Original Message:

Posted by: Sadat Hussain ( )
Organization:Nortel Networks
Date posted: Tue Mar 5 14:48:48 US/Eastern 2002
Subject: ASIC Soft Errors
I need to know how soft errors happen in either ASIC memory or flip flops. What are some typical ASIC soft error rates? Compared to hard or "stuck at" faults how do SERs affect the reliability of an ASIC?


Subject: Single event latch-up
Reply Posted by: B.W.Dudley ( )
Organization: RAC
Date Posted: Thu Mar 14 15:00:53 US/Eastern 2002
Searched and found a very interesting paper by Mr. W.E. Willing called "Combining Single Event Latch-up and Reliability Requirements for Space Vehicles. This paper, published in the 1995 Proceeding annual Reliability and Maintainability Symposium, describes a technique to combine the predicted values for the memory devices with the up-set failure rate. This is some excellent work on a difficult subject. Single event effects are caused by the passage of high energy highly ionizing charged particles through vulnerable regions of integrated circuits. The key parameter, which characterizes the susceptibility of an integrated circuit to a single event effect is the threshold linear energy transfer. This energy transfer is a measurement of the ionization density along the path of a particle traversing the integrated circuit and for a given sensitive region in the integrated circuit. The amount of deposited charge in that region is directly proportional to the linear energy transfer. Up-sets are a function of the energy transfer and cross section of the device in cm per bit and the particles per cm^2 per day. For example, a MT5C1008 SRAM has 4 x 10^-8 single event latch ups per device per day x 1/24 x 1000000. This equals 1.6 latch-ups per billion hours which can be combined with the estimated random defect failure rate of 15 failures per billion hours. The result is an estimate for the device of 16.6 failures per billion hours.

Reply to this message