Forum: Reliability & Maintainability Questions and Answers

Topic: Reliability & Maintainability Questions and Answers

Topic Posted by: Reliability & Maintainability Forum ( )
Organization: System Reliability Center
Date Posted: Mon Aug 31 12:47:36 US/Eastern 1998

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Posted by: HENSENS ( )
Date posted: Thu Dec 12 8:07:21 US/Eastern 2002
Subject: ASIC FMECA - Main failure modes
I am searching information for doing an internal FMECA analysis of a digital ASIC in CMOS 0.6Ám technology. What about the common approach for analysing the contribution of internal functions of an integrated circuit in failure rate ? Does anybody know if they are existing publications or research results highlighting the main internal failure modes observed in ASIC or integrated circuits during operation (as stuck-at-0 or stuck-at-1, supply short circuit, buffer output short cicuit,...) ? Is the main failure mode of the CMOS transistor predictable (open drain, short circuit or leakage drain-source,...) or random ? Is the short-circuit between positive/negative supply tracks (through interlayer oxide breakdown) a significant / predominant failure mode in current integrated circuits ? I thank you in advance for any help you could give in this way.


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