System Reliability Center - R&M Library

ELECTRO-THERMAL OVERSTRESS FAILURE IN MICROELECTRONICS, FINAL TECHNICAL REPORT

FAILURE MICROELECTRONIC CIRCUITS CAUSED BY ELECTRICAL OVERSTRESS HAS BEEN INVESTIGATED THEORETICALLY AND EXPERIMENTALLY. COMPUTER CALCULATIONS ON HEAT FLOW IN SILICON STRUCTURES HAVE POINTED OUT THE NECESSITY OF USING TEMPERATURE DEPENDENT THERMAL CONSTANTS FOR SILICON. THE EFFECT OF SURFACE LAYERS AND POWER DISTRIBUTION ON THE PEAK TEMPERATURE IN SILICON DEVICES UNDER TRANSIENT CONDITIONS HAS BEEN INVESTIGATED. THE CONTRACTOR PERFORMED A COMBINED ANALYTICAL AND EXPERIMENTAL PROGRAM TO DEFINE THE SIGNIFICANT PARAMETERS ASSOCIATED WITH OVERSTRESS FAILURE OF MICROELECTRONIC STRUCTURES.

Year 2000 Initiatives at the Pacific Missile Range Facility

The overall audit objective was to determine whether the year 2000 initiatives at the Pacific Missile Range Facility to address the year 2000 computer problems were effective and whether they complied with the DoD Year 2000 Management Plan. Specifically, we determined whether the Pacific Missile Range Facility resolved and reported date processing issues for potential year 2000 related system failures that could affect the Navy's test and evaluation activities.

552ND Air Control Wing Year 2000 Infrastructure Program for the Airborne Warning and Control System

The overall audit objective was to determine whether the 552nd Air Control Wing effectively planned, executed, and coordinated year 2000 infrastructure efforts for the Airborne Warning and Control System. Specifically, we reviewed the 552nd Air Control Wing year 2000 infrastructure program management plan; contingency and test plans; funding for replacing, renovating, and repairing year 2000 noncompliant systems; and the system certification processes.

TEST SPECIFICATIONS FOR HYBRID MICROELECTRONICS

THESE FIELD EXPERIENCE DATA ARE ON THE HYBRID AND MONOLITHIC DTL DEVICES IN THE FLIGHT GUIDANCE SYSTEM OF THE MCDONNELL DOUGLAS DC-10 AIRCRAFT. FAILURE RATES ARE GIVEN. ALSO INCLUDED ARE TEST SPECIFICATIONS FOR HYBRID MICROELECTRONICS.

Army Research Laboratory Preparation for Year 2000

The overall audit objective was to determine whether the Army Research Laboratory is adequately preparing its information technology systems to resolve date-processing issues regarding the year 2000 computing problem. Specifically, the audit determined whether the Army Research Laboratory complied with the DoD Year 2000 Management Plan and the Army Year 2000 Action Plan.

Shoulder-Launched Multiple-Purpose Assault Weapon

This invention pertains to a shoulder-launched multiple-purpose assault weapon having a modified spotter rifle with a top-mounted rocket launcher tube is provided. The spotter rifle forms the base structure of the weapon and all weapon controls are located on the spotter rifle. The spotter rifle has several dual-function mechanisms which perform the combined functions of assembly and safing, bolt-locking back and cartridge ejecting, simultaneous adjustment of both open and optical sights, firing, selectively, of both the spotter round and the rocket round. The combination of these dual-firing mechanisms provides a lighter weight, better-balanced and smaller weapon. The reduction in parts count improves reliability and lowers cost. Other improved features include an adjustable spotter rifle barrel used to match the boresight of the rocket tube and an improved locking mechanism. A dual function trigger assembly operated two sears from a single trigger. The primary sear operates a rotating type hammer while the secondary sear operates a plunger-type hammer. The hammers fire, respectively, the spotter rifle and the rocket

Management of the Defense Technology Security Administration Year 2000 Program

Our overall objective was to determine whether planning and management within the Defense Technology Security Administration were adequate to ensure that continuity of operations will not be unduly disrupted by year 2000 related issues. Specifically, the audit addressed the actions taken by the Defense Technology Security Administration to resolve date-processing issues regarding the year 2000, as well as preparation of plans to address year 2000 related system failures that could impact the ability of the Defense Threat Reduction Agency to perform its mission.

DETERMINATION OF OPTIMUM BURN-IN TIME - A COMPOSITE CRITERION

THE OBJECT OF THIS PAPER IS TO PRESENT MATHEMATICAL MODEL CAPABLE OF DETERMINING THE OPTIMUM AMOUNT OF TIME SEMICONDUCTOR DEVICES, EXHIBITING SPECIFIED LIFE CHARACTERISTICS, MUST BE PLACED ON BURN-IN TO OBTAIN A MAXIMUM MEASURE OF PERFORMANCE VERSUS TOTAL COST. TO MAKE THE MODEL UNUSUALLY OPERATIONAL AND REALISTIC, THE TRADITIONAL ASSUMPTION OF AN EXPONENTIAL (MORE RECENTLY, WEIBULL) DISTRIBUTION OF LIFE IS OMITTED IN FAVOR OF THE GENERALIZED GAMMA DISTRIBUTION (GGD).

RLOGIN(1): The Untold Story

Coding defects account for a significant portion of the reports received by the CERT(registered) Coordination Center. Through in-depth analysis of these reports and generalizing our findings from those analyses, we have begun to create guidelines for mitigation strategies for existing defects and avoidance strategies when coding new software. In this document, we report the results of our analysis of the well known defect in the rlogin program. We discuss the coding defect in detail, three mitigation strategies devised to remedy the defect, and two avoidance strategies offered as a guide to reducing the instances of similar coding defects in new programs. We end with three design notes aimed at eliminating these defects at the hardware and protocol design

A Study of Practice Issues in Model-Based Verification Using the Symbolic Model Verifier (SMV)

This report presents the results of a case study into practice issues involved in using the Symbolic Model Verifier (SMV) for model checking software systems. The case study is of a Simplex implementation-the Simplex coordinated demonstration system for reliable system upgrade. The investigation consisted of generating a system model (using both statechart and SMV notations), specifying claims (expected properties) of the system as temporal logic formulae, and checking those formulae with respect to the SMV model. The various steps involved in the modeling process are described. Examples of the claims, their results, and a description of how the SMV tool analyzed them are detailed. Key engineering decisions made during the modeling process and a work breakdown of the effort are also presented.

next 10 >>

For guidance on how to use this to obtain documents please refer to Obtaining Documents.